1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor integrated circuit device having a transistor and, more particularly, to a method of manufacturing a high-speed, high-integration density semiconductor integrated circuit device.
2. Description of the Related Art
An SST-1A process, which is developed by NTT (Nihon Telephone and Telegram Inc.), is known as a conventional method of manufacturing a bipolar transistor. This process is described in IEDM-INTERNATIONAL ELECTRON DEVICES MEETING, 1983, pp. 16, T. Sakai and M. Suzuki.
In the conventional method of manufacturing a transistor using the above SST-IA process, however, when a high-speed element (e.g., a bipolar transistor) is to be formed, various problems are posed, i.e., impurity redistribution occurs, high-precision control of the depth and carrier density distribution of an active layer is difficult, and the manufacturing cost is increased.
The above impurity redistribution occurs because a donor is diffused from an n.sup.+ -type buried region toward an overlying n.sup.- -type epitaxial layer. A thin epitaxial layer disappears because of this impurity redistribution. In addition, the carrier density distribution of the n.sup.- -type collector region composed of the epitaxial layer is disturbed due to the influences of the diffusion of the donor. For this reason, it is difficult to control the carrier density distribution of the collector region.
The high precision control of the depth and the carrier density distribution of the active layer is difficult for the following reasons. In the SST-1A process, ion-implantation is employed as a method of forming a base region. However, if impurity ions are deeply implanted into a substrate by using the ion-implantation method, the impurity distribution is widely spread. For this reason, it is difficult to obtain a desired carrier density distribution. Furthermore, in order to obtain a steep distribution curve of the implanted impurity, the impurity must be diffused by annealing after ion-implantation is performed at a low acceleration energy. At the same time, this region must be activated to obtain a desired carrier density distribution. However, it is difficult to control the carrier density distribution by utilizing such a method, and moreover, impurity redistribution is caused during the annealing process.
The manufacturing cost is increased because of the following reasons. Since formation of a thin, uniform epitaxial layer on a semiconductor wafer and of a buried layer is difficult, the cost of wafer is inevitably increased. In addition, when a semiconductor element is to be formed in such a wafer, element isolation must be performed by using an element isolation technique requiring a complicated process such as trench isolation. Therefore, the manufacturing cost is increased in this respect as well.